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FPGA

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Ethernet

Pin
  1. alexforencich/verilog-ethernet

Reading List

Pin
  1. Beginners Guide To Clock Data Recovery
  2. Implementation of glitch free clock switching logic
  3. Clock mux for allowing glitch-free muxing of asynchronous clocks
  4. Clock Switching
  5. Clock and Data Recovery/Buffer Memory (Elastic Buffer)

Simulation

Pin
  1. Creating automated testbenches for your digital designs using python and iverilog
  2. New bookmark
  3. Performing a Functional Simulation with the ModelSim-Altera Software
  4. Preparing for EDA Simulation

Misc

Pin
  1. Pipeline Skid Buffer
  2. Ones count system-verilog
  3. Count the number of 1's in a Binary number - Verilog Implementation with Testbench
  4. PPM to Hz Calculator
  5. better FPGA design. - Clock Dividers
  6. Quartus, timing closure: Obtaining a concise multi-corner timing path report
  7. 4 more

Projects to look at

Pin
  1. Circular Buffer
  2. GitHub - olofk/wb_intercon: Wishbone interconnect utilities
  3. xesscorp/VHDL_Lib
  4. olofk/fifo
  5. sd card controller
  6. Verification Of FIFO Part
  7. 4 more

Videos

Pin
  1. Machine Learning on FPGAs: Neural Networks

Projects

Pin
  1. ECE 5760: Conway's Game of Life
  2. Building an SDR from scratch
  3. LCD Controller - How to control a laptop LCD panel with an FPGA

de0-nano

Pin
  1. FPGA to VGA using DE0-Nano | Gerfficient

vga

Pin
  1. FPGA to VGA using DE0-Nano | Gerfficient

Soft Cores

Pin
  1. Microblaze Qemu U-BOOT
  2. PetaLinux
  3. Getting Started with OpenRISC
  4. qemu
  5. Designing a CPU in VHDL, Part 1: Rationale, tools, method

Dev Boards

Pin
  1. Cheap FPGA Development Boards
  2. DE0-Nano Power Supply Upgrade
  3. 96Boards

OpenCL

Pin
  1. fccm16-tinker.pdf
  2. Intel® FPGA SDK for OpenCL™
  3. iwocl14.pdf
  4. OpenCL Mandelbrot Demo on Atlas-SoC

verilog

Pin
  1. SystemVerilog Functions - Verification Guide
  2. FIFO(First In First Out) Buffer in Verilog
  3. Verilog Arrays Plain and Simple - Verilog Pro
  4. How to Pack Data Using the SystemVerilog Streaming Operators (>>,
  5. How to efficiently implement a single output pulse from a long input on Altera?
  6. includes.pdf
  7. 9 more

Papers

Pin
  1. Greczner_Meng_Final.pdf
  2. Fan_Master_Thesis.pdf
  3. FPGA Clock Schemes - Embedded.com
  4. qts_qii51006.pdf
  5. slaa594a.pdf
  6. 10_01_074_078.pdf

System Verilog

Pin
  1. FPGA

Blaster Clone

Pin
  1. USB-Blasterもどきの製作

Kernel

Pin
  1. Robert Love Kernel QnA

Modelsim

Pin
  1. ModelSim Compile Script
  2. Note Myself: ModelSim Failed to access library 'work'
  3. Using Modelsim for Simulation, For Beginners

Projects

Pin
  1. hamsternz - Overview
  2. mattvenn/TinyFPGA-BX
  3. Design and Implementation of SD Host Controller IP Core
  4. Apple2fpga: Reconstructing an Apple II+ on an FPGA
  5. ultraembedded/cores

Storage

Pin
  1. emb4fun

Quartus II

Pin
  1. Electronics - Quartus II - Using command-line interface (CLI)

Compression

Pin
  1. DEFLATE :: Overview :: OpenCores
  2. An Explanation of the `Deflate' Algorithm
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